1. Field of the Invention
The present invention relates to a dynamic address translation (below, DAT) processing apparatus in a data processing system, and particularly, it relates to a DAT processing apparatus enabling high speed updating of a change bit contained in a page table entry stored in a main memory to improve performance of a data processing system.
2. Description of the Related Art
Virtual memory systems are widely used in data processing systems. In a virtual memory system, a programmer can easily write a program, by use of a virtual address space, which uses a considerably larger memory capacity than that of the main memory. Therefore, when the programmer writes a program, he need not consider the capacity of the main memory. In this case, the DAT processing apparatus is provided in hardware (i.e., a central processing unit and a main memory) in the data processing system to realize the virtual memory system.
The virtual address space is held in logical memory which includes the main memory and all external memories, however only the main memory can be accessed from the central processing unit (CPU) in the hardware. Accordingly, when the CPU accesses a memory location which does not exist in the main memory, that memory location must be moved to the main memory.
The DAT processing apparatus converts a virtual address contained in an instruction of a program to a real address physically stored in the main memory. In the DAT processing apparatus, the main memory is divided into a plurality of page units. The virtual address space is also divided into a plurality of page units to correspond to pages of the main memory.
The virtual address space is further divided into a plurality of segment units, each larger than the page unit. That is, one segment is formed by several page units. Further, the virtual address memory is divided into access units for several steps each larger than a segment unit.
An explanation is given hereinafter of the DAT operation in the case of two access steps, i.e., the page and segment, in this specification.